vqrshl

Vector Saturating Rounding Shift Left

VQRSHL<c>.<dt> <Qd>, <Qm>, <Qn>

Shifts left with saturation and rounding.

Details

Vector Saturating Rounding Shift Left shifts each element in Qm left by the amount specified in the corresponding element of Qn, with saturation and rounding applied. When the shift amount is negative, a right shift with rounding is performed. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.

Pseudocode Operation

for i = 0 to elements-1 do
  shift_amount ← SignExtend(Qn[i])
  if shift_amount >= 0 then
    result ← SatQ(Qm[i] << shift_amount, esize)
  else
    rounding_bit ← Qm[i][(-shift_amount-1)]
    shifted ← Qm[i] >> (-shift_amount)
    result ← SatQ(shifted + rounding_bit, esize)
  Qd[i] ← result

Example

VQRSHL.dt q0, q2, q1

Encoding

Binary Layout
1111001
U
0
D
size
Vn
Vd
0101
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000510
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register
  • Qn
    Shift Reg

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000510 VQRSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn> A32 1111001 | U | 0 | D | size | Vn | Vd | 0101 | N | 0 | M | 1 | Vm
0xF2000550 VQRSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn> A32 1111001 | U | 0 | D | size | Vn | Vd | 0101 | N | 1 | M | 1 | Vm
0xEF000510 VQRSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn> T32 111 | U | 11110 | D | size | Vn | Vd | 0101 | N | 0 | M | 1 | Vm
0xEF000550 VQRSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn> T32 111 | U | 11110 | D | size | Vn | Vd | 0101 | N | 1 | M | 1 | Vm

Description

Vector Saturating Rounding Shift Left takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. For truncated results see VQSHL (register). The first operand and result elements are the same data type, and can be any one of: The second operand is a signed integer of the same size. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    bits(esize) result;
    boolean sat;
    for r = 0 to regs-1
        for e = 0 to elements-1
            integer element = Int(Elem[D[m+r], e, esize], unsigned);
            integer shift = SInt(Elem[D[n+r], e, esize]<7:0>);
            if shift >= 0 then // left shift
                element = element << shift;
            else               // rounding right shift
                shift = -shift;
                element = (element + (1 << (shift - 1))) >> shift;
            (result, sat) = SatQ(element, esize, unsigned);
            Elem[D[d+r], e, esize] = result;
            if sat then FPSCR.QC = '1';