and

Vector Bitwise AND

AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Bitwise AND of two vectors.

Details

The Vector Bitwise AND instruction bitwise AND of two vectors.

Pseudocode Operation

Vd ← Vn AND Vm

Example

AND v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
00
1
Rm
0001
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E201C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register