and

Vector Bitwise AND

AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Bitwise AND of two vectors.

Details

Performs bitwise AND between corresponding elements of Vn and Vm, storing results in Vd. Operates on the full vector width without regard to element size. The Q bit determines operation width (64-bit for Q=0, 128-bit for Q=1). No condition flags are affected. AArch64 NEON extension.

Pseudocode Operation

for i = 0 to (128 >> (if Q then 0 else 1)) - 1:
  Vd[i] ← Vn[i] AND Vm[i];

Example

AND v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
00
1
Rm
00011
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E201C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E201C00 AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 00 | 1 | Rm | 00011 | 1 | Rn | Rd
0x12000000 AND <Wd|WSP>, <Wn>, #<imm> A64 0 | 00 | 100100 | 0 | immr | imms | Rn | Rd
0x92000000 AND <Xd|SP>, <Xn>, #<imm> A64 1 | 00 | 100100 | N | immr | imms | Rn | Rd
0x0A000000 AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 00 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x8A000000 AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 00 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x25004000 AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 0 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 0 | Pd
0x041A0000 AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 011 | 01 | 0 | 000 | Pg | Zm | Zdn
0x05800000 AND <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 1 | 0 | 0000 | imm13 | Zdn
0x04203000 AND <Zd>.D, <Zn>.D, <Zm>.D A64 00000100 | 0 | 0 | 1 | Zm | 001100 | Zn | Zd

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;


result = operand1 AND operand2;
V[d, datasize] = result;