fcmla
Floating-Point Complex Multiply Accumulate (NEON)
Complex multiply-accumulate with rotation (NEON).
Pseudocode Operation
// rot encodes: 0→0°, 1→90°, 2→180°, 3→270°
for i = 0 to 1 do
rotated ← ComplexRotate(Vm.S[2*i:2*i+1], rot)
product ← ComplexMultiply(Vn.S[2*i:2*i+1], rotated)
Vd.S[2*i:2*i+1] ← Vd.S[2*i:2*i+1] + product
endforExample
Encoding
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register -
rot
Rot
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x2F001000 | FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate> | A64 | 0 | Q | 1 | 01111 | size | L | M | Rm | 0 | rot | 1 | H | 0 | Rn | Rd | ||
| 0x2E00C400 | FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate> | A64 | 0 | Q | 1 | 01110 | size | 0 | Rm | 110 | rot | 1 | Rn | Rd | ||
| 0x64000000 | FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const> | A64 | 01100100 | size | 0 | Zm | 0 | rot | Pg | Zn | Zda | ||
| 0x64A01000 | FCMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const> | A64 | 01100100 | 1 | 0 | 1 | i2 | Zm | 0001 | rot | Zn | Zda | ||
| 0x64E01000 | FCMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const> | A64 | 01100100 | 1 | 1 | 1 | i1 | Zm | 0001 | rot | Zn | Zda |
Description
Floating-point Complex Multiply Accumulate. This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers and the destination register: The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) operand3 = V[d, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) element3;
bits(esize) element4;
for e = 0 to (elements DIV 2)-1
case rot of
when '00'
element1 = Elem[operand2, e*2, esize];
element2 = Elem[operand1, e*2, esize];
element3 = Elem[operand2, e*2+1, esize];
element4 = Elem[operand1, e*2, esize];
when '01'
element1 = FPNeg(Elem[operand2, e*2+1, esize], FPCR);
element2 = Elem[operand1, e*2+1, esize];
element3 = Elem[operand2, e*2, esize];
element4 = Elem[operand1, e*2+1, esize];
when '10'
element1 = FPNeg(Elem[operand2, e*2, esize], FPCR);
element2 = Elem[operand1, e*2, esize];
element3 = FPNeg(Elem[operand2, e*2+1, esize], FPCR);
element4 = Elem[operand1, e*2, esize];
when '11'
element1 = Elem[operand2, e*2+1, esize];
element2 = Elem[operand1, e*2+1, esize];
element3 = FPNeg(Elem[operand2, e*2, esize], FPCR);
element4 = Elem[operand1, e*2+1, esize];
Elem[result, e*2, esize] = FPMulAdd(Elem[operand3, e*2, esize], element2, element1, FPCR);
Elem[result, e*2+1, esize] = FPMulAdd(Elem[operand3, e*2+1, esize], element4, element3, FPCR);
V[d, datasize] = result;