sxtb

Signed Extend Byte (A32)

SXTB<c> <Rd>, <Rm> {, <rotation>}

Sign-extends the low byte (8-bits) to 32-bits.

Pseudocode Operation

rotated ← ROR(Rm, rotation)
Rd ← SignExtend(rotated[7:0], 32)

Example

SXTB r0, r2

Encoding

Binary Layout
cond
31:28
01101
27:23
0
22
10
21:20
1111
19:16
Rd
15:12
rotate
11:10
0
9
0
8
0111
7:4
Rm
3:0
 
Format Data Proc
Opcode 0x06AF0070
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register

Related

Other forms of sxtb

  • sxtb Signed Extend Byte (Thumb)
  • sxtb Sign Extend Byte

Across architectures

Sign Extend Byte : how x86, ARM, RISC-V, and PowerISA each do this.

More in A32 (Base)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06AF0070 SXTB{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>} A32 cond | 01101 | 0 | 10 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm
0xB240 SXTB{<c>}{<q>} {<Rd>,} <Rm> T32 10110010 | 0 | 1 | Rm | Rd
0xFA4FF080 SXTB{<c>}.W {<Rd>,} <Rm> T32 111110100 | 10 | 0 | 1111 | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Signed Extend Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = SignExtend(rotated<7:0>, 32);