smulwt
Signed Multiply (Word x Top)
SMULWT<c> <Rd>, <Rn>, <Rm>
Multiplies 32-bit Rn by top 16-bits of Rm, takes top 32-bits of result.
Details
Signed multiply of the 32-bit Rn by the top 16-bit halfword of Rm, extracting the top 32 bits of the 48-bit product into Rd. This is an A32 DSP instruction that produces no flag changes; overflow is not indicated.
Pseudocode Operation
product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[31:16], 48);
Rd ← product[47:16];Example
SMULWT r0, r1, r2
Encoding
Binary Layout
cond
00010
01
0
Rd
0000
Rm
1
1
1
0
Rn
Operands
-
Rd
Destination general-purpose register -
Rn
Word Src -
Rm
Half Src
Reference (Arm AArch32 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x012000E0 | SMULWT{<c>}{<q>} {<Rd>,} <Rn>, <Rm> | A32 | cond | 00010 | 01 | 0 | Rd | 0000 | Rm | 1 | 1 | 1 | 0 | Rn | ||
| 0xFB30F010 | SMULWT{<c>}{<q>} {<Rd>,} <Rn>, <Rm> | T32 | 111110110 | 011 | Rn | 1111 | Rd | 00 | 0 | 1 | Rm |
Description
Signed Multiply (word by halfword) multiplies a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are written to the destination register. The bottom 16 bits of the 48-bit product are ignored. No overflow is possible during this instruction.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
product = SInt(R[n]) * SInt(operand2);
R[d] = product<47:16>;
// Signed overflow cannot occur