smull

Signed Multiply Long

SMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts>

Multiplies signed narrow vectors, producing wider result.

Details

The Signed Multiply Long instruction multiplies signed narrow vectors, producing wider result.

Pseudocode Operation

Vd ← Vn × Vm

Example

SMULL v0.4s.Td, v1.4s.Ts, v2.4s.Ts

Encoding

Binary Layout
0
Q
001110
size
1
0000
Rm
1100
Rn
Rd
 
Format SIMD Three Register Diff
Opcode 0x0E20C000
Extension NEON (SIMD)

Operands

  • Vd
    Dest (Wide)
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register