subs

Subtract and Return (A32)

SUBS PC, LR, #<imm>

Subs PC, LR, #imm (Exception return mechanism).

Pseudocode Operation

result ← LR - imm12
N ← result[31]
Z ← (result == 0)
C ← (LR >= imm12)  
V ← OverflowFrom(LR - imm12)
PC ← result
CPSR ← SPSR

Example

SUBS PC, LR, #16

Encoding

Binary Layout

cond

31:28

0010

27:24

010

23:21

1

20

Rn

19:16

Rd

15:12

imm12

11:0

 

Format Data Proc

Opcode 0x02500000

Extension A32 (Base)

Operands

• imm
  Signed immediate value

Related

Other forms of subs

• subs Subtract and Set Flags (Extended)
• subs Subtract and Set Flags (Immediate)
• subs Subtract and Set Flags (Shifted)

More in A32 (Base)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x02500000	SUBS{<c>}{<q>} {<Rd>,} <Rn>, #<const>		A32		cond | 0010 | 010 | 1 | Rn | Rd | imm12
0xF1B00000	SUBS.W {<Rd>,} <Rn>, #<const>		T32		11110 | i | 0 | 1101 | 1 | Rn | 0 | imm3 | Rd | imm8
0xF3D08F00	SUBS{<c>}{<q>} PC, LR, #<imm8>		T32		111100111101 | Rn | 10 | 0 | 0 | 1 | 1 | 1 | 1 | imm8
0x00500060	SUBS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX		A32		cond | 0000 | 010 | 1 | Rn | Rd | 00000 | 11 | 0 | Rm
0x00500000	SUBS{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}		A32		cond | 0000 | 010 | 1 | Rn | Rd | imm5 | stype | 0 | Rm
0xEBB00030	SUBS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX		T32		1110101 | 1101 | 1 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEBB00000	SUBS.W {<Rd>,} <Rn>, <Rm>		T32		1110101 | 1101 | 1 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm
0x00500010	SUBS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs>		A32		cond | 0000 | 010 | 1 | Rn | Rd | Rs | 0 | stype | 1 | Rm
0x025D0000	SUBS{<c>}{<q>} {<Rd>,} SP, #<const>		A32		cond | 0010 | 010 | 1 | 1101 | Rd | imm12
0xF1BD0000	SUBS{<c>}{<q>} {<Rd>,} SP, #<const>		T32		11110 | i | 0 | 1101 | 1 | 1101 | 0 | imm3 | Rd | imm8
0x005D0060	SUBS{<c>}{<q>} {<Rd>,} SP, <Rm> , RRX		A32		cond | 0000 | 010 | 1 | 1101 | Rd | 00000 | 11 | 0 | Rm
0x005D0000	SUBS{<c>}{<q>} {<Rd>,} SP, <Rm> {, <shift> #<amount>}		A32		cond | 0000 | 010 | 1 | 1101 | Rd | imm5 | stype | 0 | Rm
0xEBBD0030	SUBS{<c>}{<q>} {<Rd>,} SP, <Rm>, RRX		T32		1110101 | 1101 | 1 | 1101 | 0 | 000 | Rd | 00 | 11 | Rm
0xEBBD0000	SUBS{<c>}{<q>} {<Rd>,} SP, <Rm> {, <shift> #<amount>}		T32		1110101 | 1101 | 1 | 1101 | 0 | imm3 | Rd | imm2 | stype | Rm

Description

Subtract (immediate) subtracts an immediate value from a register value, and writes the result to the destination register. If the destination register is not the PC, the SUBS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (result, nzcv) = AddWithCarry(R[n], NOT(imm32), '1');
    if d == 15 then
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;