str

Store Register (Register)

STR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Stores a register to memory (Register offset).

Pseudocode Operation

offset ← ExtendValue(Rm, option, S)
address ← Xn + offset
[address] ← Wt[31:0]

Example

STR w3, [x1, Rm ]

Encoding

Binary Layout
10
31:30
111
29:27
0
26
00
25:24
00
23:22
1
21
Rm
20:16
option
15:13
S
12
10
11:10
Rn
9:5
Rt
4:0
 
Format Load/Store Reg
Opcode 0xB8200800
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • Rm
    Offset Reg

Related

Other forms of str

  • str Store SIMD&FP Register (Immediate)
  • str Store Register (Immediate)
  • str Store Register (A32)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x3C000400 STR <Bt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0x7C000400 STR <Ht>, [<Xn|SP>], #<simm> A64 01 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0xBC000400 STR <St>, [<Xn|SP>], #<simm> A64 10 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0xFC000400 STR <Dt>, [<Xn|SP>], #<simm> A64 11 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0x3C800400 STR <Qt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 10 | 0 | imm9 | 01 | Rn | Rt
0x3C000C00 STR <Bt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0x7C000C00 STR <Ht>, [<Xn|SP>, #<simm>]! A64 01 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0xBC000C00 STR <St>, [<Xn|SP>, #<simm>]! A64 10 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0xFC000C00 STR <Dt>, [<Xn|SP>, #<simm>]! A64 11 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0x3C800C00 STR <Qt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 10 | 0 | imm9 | 11 | Rn | Rt
0x3D000000 STR <Bt>, [<Xn|SP>{, #<pimm>}] A64 00 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0x7D000000 STR <Ht>, [<Xn|SP>{, #<pimm>}] A64 01 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0xBD000000 STR <St>, [<Xn|SP>{, #<pimm>}] A64 10 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0xFD000000 STR <Dt>, [<Xn|SP>{, #<pimm>}] A64 11 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt

Description

Store Register (register) calculates an address from a base register value and an offset register value, and stores a 32-bit word or a 64-bit doubleword to the calculated address, from a register. For information about memory accesses, see Load/Store addressing modes. The instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an offset register value. The offset can be optionally shifted and extended.

Operation

bits(64) offset = ExtendReg(m, extend_type, shift, 64);
bits(64) address;
bits(datasize) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, TRUE);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = X[t, datasize];
Mem[address, datasize DIV 8, accdesc] = data;