str

Store Register (A32)

STR<c> <Rt>, [<Rn>, #+/-<imm>]{!}

Stores a word to memory.

Pseudocode Operation

offset ← if U then imm12 else -imm12 endif;
if P then
  address ← Rn + offset;
else
  address ← Rn;
endif;
Memory[address] ← Rt;
if P == 0 or W then
  Rn ← Rn + offset;
endif;

Example

STR r3, [r1, #+/-#16]!

Encoding

Binary Layout
cond
31:28
010
27:25
0
24
U
23
0
22
0
21
0
20
Rn
19:16
Rt
15:12
imm12
11:0
 
Format Load/Store
Opcode 0x04000000
Extension A32 (Base)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Related

Other forms of str

  • str Store SIMD&FP Register (Immediate)
  • str Store Register (Immediate)
  • str Store Register (Register)

More in A32 (Base)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x05000000 STR{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}] A32 cond | 010 | 1 | U | 0 | 0 | 0 | Rn | Rt | imm12
0x04000000 STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> A32 cond | 010 | 0 | U | 0 | 0 | 0 | Rn | Rt | imm12
0x05200000 STR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! A32 cond | 010 | 1 | U | 0 | 1 | 0 | Rn | Rt | imm12
0x6000 STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] T32 011 | 0 | 0 | imm5 | Rn | Rt
0x9000 STR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] T32 1001 | 0 | Rt | imm8
0xF8C00000 STR{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}] T32 111110001 | 10 | 0 | Rn | Rt | imm12
0xF8400C00 STR{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}] T32 111110000 | 10 | 0 | Rn | Rt | 1 | 1 | 0 | 0 | imm8
0xF8400900 STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> T32 111110000 | 10 | 0 | Rn | Rt | 1 | 0 | U | 1 | imm8
0xF8400D00 STR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! T32 111110000 | 10 | 0 | Rn | Rt | 1 | 1 | U | 1 | imm8
0x07000000 STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] A32 cond | 011 | 1 | U | 0 | 0 | 0 | Rn | Rt | imm5 | stype | 0 | Rm
0x06000000 STR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} A32 cond | 011 | 0 | U | 0 | 0 | 0 | Rn | Rt | imm5 | stype | 0 | Rm
0x07200000 STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! A32 cond | 011 | 1 | U | 0 | 1 | 0 | Rn | Rt | imm5 | stype | 0 | Rm
0x5000 STR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] T32 0101 | 0 | 0 | 0 | Rm | Rn | Rt
0xF8400000 STR{<c>}.W <Rt>, [<Rn>, {+}<Rm>] T32 111110000 | 10 | 0 | Rn | Rt | 000000 | imm2 | Rm

Description

Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

Operation

if CurrentInstrSet() == InstrSet_A32 then
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
        if wback then R[n] = offset_addr;
else
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        MemU[address,4] = R[t];
        if wback then R[n] = offset_addr;