vrev64

Vector Reverse 64

VREV64<c>.<dt> <Qd>, <Qm>

Reverses elements within 64-bit doublewords.

Details

Reverses the order of elements within each 64-bit doubleword in the source register. The granularity of reversal depends on element size: 8-bit elements are reversed within 64-bit units, 16-bit elements are reversed within 64-bit units, and 32-bit elements are reversed within 64-bit units. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.

Pseudocode Operation

if element_size == 8:
  for i = 0 to 127 by 64:
    for j = 0 to 63 by 8:
      Qd[i+j+7:i+j] ← Qm[i+63-j:i+56-j]
else if element_size == 16:
  for i = 0 to 127 by 64:
    for j = 0 to 48 by 16:
      Qd[i+j+15:i+j] ← Qm[i+63-j:i+48-j]
else if element_size == 32:
  for i = 0 to 127 by 64:
    Qd[i+63:i+32] ← Qm[i+31:i+0]
    Qd[i+31:i+0] ← Qm[i+63:i+32]

Example

VREV64.dt q0, q2

Encoding

Binary Layout
111100111
D
11
size
00
Vd
0
00
00
0
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xF3B00000
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B00000 VREV64{<c>}{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 00 | 0 | M | 0 | Vm
0xF3B00040 VREV64{<c>}{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 00 | 1 | M | 0 | Vm
0xFFB00000 VREV64{<c>}{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 00 | Vd | 0 | 00 | 00 | 0 | M | 0 | Vm
0xFFB00040 VREV64{<c>}{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 00 | Vd | 0 | 00 | 00 | 1 | M | 0 | Vm

Description

Vector Reverse in doublewords reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector, and places the result in the corresponding destination vector. There is no distinction between data types, other than size. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();

    bits(64) result;
    integer element;
    integer rev_element;
    for r = 0 to regs-1
        element = 0;
        for c = 0 to containers-1
            rev_element = (element + elements_per_container) - 1;
            for e = 0 to elements_per_container-1
                Elem[result, rev_element, esize] = Elem[D[m+r], element, esize];
                element = element + 1;
                rev_element = rev_element - 1;
        D[d+r] = result;