stlxrb

Store-Release Exclusive Register Byte

STLXRB <Ws>, <Wt>, [<Xn|SP>]

Stores a byte with Release Exclusive semantics.

Details

Attempts an exclusive store of a byte from Wt to memory at the address in Xn with Release semantics, writing 0 to Ws if successful or 1 if the exclusive monitor was not held. This is an AArch64-only instruction used for atomic byte operations. No condition flags are affected.

Pseudocode Operation

if ExclusiveMonitorHeld(Xn) then { [Xn] ← Wt<7:0>; Ws ← 0; Release semantics applied } else { Ws ← 1 }

Example

STLXRB w6, w3, [x1]

Encoding

Binary Layout
00
0010000
0
0
Rs
1
11111
Rn
Rt
 
Format Load/Store Excl
Opcode 0x0800FC00
Extension Base (Atomic)

Operands

  • Ws
    Status
  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0800FC00 STLXRB <Ws>, <Wt>, [<Xn|SP>{, #0}] A64 00 | 0010000 | 0 | 0 | Rs | 1 | 11111 | Rn | Rt

Description

Store-Release Exclusive Register Byte stores a byte from a 32-bit register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(8) data;

AccessDescriptor accdesc = CreateAccDescExLDST(MemOp_STORE, TRUE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
elsif rn_unknown then
    address = bits(64) UNKNOWN;
else
    address = X[n, 64];

if rt_unknown then
    data = bits(8) UNKNOWN;
else
    data = X[t, 8];

bit status = '1';
// Check whether the Exclusives monitors are set to include the
// physical memory locations corresponding to virtual address
// range [address, address+dbytes-1].

// If AArch64.ExclusiveMonitorsPass() returns FALSE and the memory address,
// if accessed, would generate a synchronous Data Abort exception, it is
// IMPLEMENTATION DEFINED whether the exception is generated.
// It is a limitation of this model that synchronous Data Aborts are never
// generated in this case, as Mem[] is not called.
// If FEAT_SPE is implemented, it is also IMPLEMENTATION DEFINED whether or not the
// physical address packet is output when permitted and when
// AArch64.ExclusiveMonitorPass() returns FALSE for a Store Exclusive instruction.
// This behavior is not reflected here due to the previously stated limitation.
if AArch64.ExclusiveMonitorsPass(address, 1, accdesc) then
    // This atomic write will be rejected if it does not refer
    // to the same physical locations after address translation.
    Mem[address, 1, accdesc] = data;
    status = ExclusiveMonitorsStatus();
X[s, 32] = ZeroExtend(status, 32);