ldxp

Load Exclusive Pair

LDXP <Wt1>, <Wt2>, [<Xn|SP>]

Loads two words as an exclusive operation.

Details

Loads two consecutive 32-bit words from memory at the address in Xn|SP and marks the physical address pair as exclusive for subsequent store-exclusive operations. No condition flags are affected. This is an AArch64-only instruction that requires Execute permission and generates an alignment fault if the address is not 8-byte aligned.

Pseudocode Operation

address ← [Xn|SP]
Wt1 ← [address]
Wt2 ← [address + 4]
ExclusiveMonitors.MarkExclusive(address, ProcessorID, 8)

Example

LDXP w3, w4, [x1]

Encoding

Binary Layout
1
0
0010000
1
1
11111
0
Rt2
Rn
Rt
 
Format Load/Store Excl
Opcode 0x887F0000
Extension Base (Atomic)

Operands

  • Wt1
    Target 1
  • Wt2
    Target 2
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x887F0000 LDXP <Wt1>, <Wt2>, [<Xn|SP>{, #0}] A64 1 | 0 | 0010000 | 1 | 1 | 11111 | 0 | Rt2 | Rn | Rt
0xC87F0000 LDXP <Xt1>, <Xt2>, [<Xn|SP>{, #0}] A64 1 | 1 | 0010000 | 1 | 1 | 11111 | 0 | Rt2 | Rn | Rt

Description

Load Exclusive Pair of Registers derives an address from a base register value, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(datasize) data;
constant integer dbytes = datasize DIV 8;

AccessDescriptor accdesc = CreateAccDescExLDST(MemOp_LOAD, FALSE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

// Tell the Exclusives monitors to record a sequence of one or more atomic
// memory reads from virtual address range [address, address+dbytes-1].
// The Exclusives monitor will only be set if all the reads are from the
// same dbytes-aligned physical address, to allow for the possibility of
// an atomicity break if the translation is changed between reads.
AArch64.SetExclusiveMonitors(address, dbytes);

if rt_unknown then
    // ConstrainedUNPREDICTABLE case
    X[t, datasize] = bits(datasize) UNKNOWN;    // In this case t = t2
elsif elsize == 32 then
    // 32-bit load exclusive pair (atomic)
    data = Mem[address, dbytes, accdesc];
    if BigEndian(accdesc.acctype) then
        X[t, datasize-elsize] = data<datasize-1:elsize>;
        X[t2, elsize] = data<elsize-1:0>;
    else
        X[t, elsize] = data<elsize-1:0>;
        X[t2, datasize-elsize] = data<datasize-1:elsize>;
else // elsize == 64
    // 64-bit load exclusive pair (not atomic), but must be 128-bit aligned
    if !IsAligned(address, dbytes) then
        AArch64.Abort(address, AlignmentFault(accdesc));

    bits(64) address2 = GenerateAddress(address, 8, accdesc);
    X[t, 64] = Mem[address, 8, accdesc];
    X[t2, 64] = Mem[address2, 8, accdesc];