sm4ekey

SM4 Key (A32)

SM4EKEY.32 <Qd>, <Qm>

SM4 key schedule step.

Pseudocode Operation

Qd ← SM4_KeySchedule(Qd, Qm)

Example

SM4EKEY.32 q0, q2

Encoding

Binary Layout

01000101

31:24

20:16

11110

15:11

9:5

4:0

Format Crypto 2-Reg

Opcode 0x4520F000

Extension Crypto (SM4)

Operands

Qd
Destination 128-bit SIMD register
Qm
Key

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xCE60C800	SM4EKEY <Vd>.4S, <Vn>.4S, <Vm>.4S		A64		11001110011 \| Rm \| 1 \| 1 \| 00 \| 10 \| Rn \| Rd
0x4520F000	SM4EKEY <Zd>.S, <Zn>.S, <Zm>.S		A64		01000101 \| 0 \| 0 \| 1 \| Zm \| 11110 \| 0 \| Zn \| Zd

Description

The SM4EKEY instruction reads four rounds of 32-bit input key values from each 128-bit segment of the first source vector, along with four rounds of 32-bit constants from the corresponding 128-bit segment of the second source vector. The four rounds of output key values are derived in accordance with the SM4 standard, and placed in the corresponding segments of the destination vector. This instruction is unpredicated. ID_AA64ZFR0_EL1.SM4 indicates whether this instruction is implemented. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer segments = VL DIV 128;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;

for s = 0 to segments-1
    bits(128) source = Elem[operand2, s, 128];
    bits(32) intval;
    bits(8) sboxout;
    bits(32) const;
    bits(128) roundresult = Elem[operand1, s, 128];

    for index = 0 to 3
        const = Elem[source, index, 32];
        intval = roundresult<127:96> EOR roundresult<95:64> EOR roundresult<63:32> EOR const;
        for i = 0 to 3
            Elem[intval, i, 8] = Sbox(Elem[intval, i, 8]);

        intval = intval EOR ROL(intval, 13) EOR ROL(intval, 23);
        intval = intval EOR roundresult<31:0>;

        roundresult<31:0> = roundresult<63:32>;
        roundresult<63:32> = roundresult<95:64>;
        roundresult<95:64> = roundresult<127:96>;
        roundresult<127:96> = intval;

    Elem[result, s, 128] = roundresult;

Z[d, VL] = result;