sha1c

SHA1 Choose (A64)

SHA1C <Qd>, <Sn>, <Vm>.4S

SHA1 hash choose (AArch64 NEON).

Details

SHA1 choose: computes SHA1 compression function's choose operation across 128-bit state, updating the state register. Takes a 32-bit scalar index and 4 × 32-bit vector of operands, producing updated 128-bit state. Requires Crypto extension. Condition flags are not affected.

Pseudocode Operation

// Simplified: SHA1C updates 128-bit state Qd with function output based on Sn and Vm
for i = 0 to 3 do
  Qd.S[i] ← SHA1Choose(Qd.S[i], Sn, Vm.S[i])
endfor

Example

SHA1C q0, s1, v2.4s.4S

Encoding

Binary Layout
01011110
00
0
Rm
0
000
00
Rn
Rd
 
Format Crypto
Opcode 0x5E000000
Extension Crypto

Operands

  • Qd
    Destination 128-bit SIMD register
  • Sn
    First source 32-bit floating-point register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E000000 SHA1C <Qd>, <Sn>, <Vm>.4S A64 01011110 | 00 | 0 | Rm | 0 | 000 | 00 | Rn | Rd

Description

SHA1 hash update (choose).

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) x = V[d, 128];
bits(32) y = V[n, 32];    // Note: 32 not 128 bits wide
bits(128) w = V[m, 128];
bits(32) t;

for e = 0 to 3
    t = SHAchoose(x<63:32>, x<95:64>, x<127:96>);
    y = y + ROL(x<31:0>, 5) + t + Elem[w, e, 32];
    x<63:32> = ROL(x<63:32>, 30);
    <y, x> = ROL(y:x, 32);
V[d, 128] = x;