strexh

Store Register Exclusive Halfword (A32)

STREXH<c> <Rd>, <Rt>, [<Rn>]

Stores a halfword if address is still exclusive.

Pseudocode Operation

address ← Rn; if ExclusiveMonitorsCheckExclusive(address, ProcessorID(), 2) then MemU[address, 2] ← Rt[15:0]; Rd ← 0; ExclusiveMonitorsClearExclusive(ProcessorID()); else Rd ← 1;

Example

STREXH r0, r3, [r1]

Encoding

Binary Layout

cond

31:28

00011

27:23

11

22:21

0

20

Rn

19:16

Rd

15:12

1

11

1

10

1

9

1

8

1001

7:4

Rt

3:0

 

Format Load/Store Excl

Opcode 0x01E00F90

Extension A32 (Atomic)

Operands

• Rd
  Status
• Rt
  Transfer general-purpose register (load/store)
• Rn
  First source / base general-purpose register

Related

Other forms of strexh

• strexh Store Register Exclusive Halfword (Thumb)

More in A32 (Atomic)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x01E00F90	STREXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]		A32		cond | 00011 | 11 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt
0xE8C00F50	STREXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]		T32		11101000110 | 0 | Rn | Rt | 1111 | 01 | 01 | Rd

Description

Store Register Exclusive Halfword derives an address from a base register value, stores a halfword from a register to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    if AArch32.ExclusiveMonitorsPass(address,2) then
        MemA[address,2] = R[t]<15:0>;
        R[d] = ZeroExtend('0', 32);
    else
        R[d] = ZeroExtend('1', 32);