vneg

Vector Negate (Double)

VNEG<c>.F64 <Dd>, <Dm>

Negates double-precision register.

Details

The Vector Negate instruction negates double-precision register.

Pseudocode Operation

// Negates double-precision register

Example

VNEG.F64 d0, d2

Encoding

Binary Layout
cond
11101011
0
D
0001
Vd
1011
01
M
0
Vm
 
Format VFP Unary
Opcode 0x0EB10B40
Extension VFP (Float)

Operands

  • Dd
    Destination 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register