ldclr

Atomic Load-Clear Word

LDCLR <Ws>, <Wt>, [<Xn|SP>]

Atomic bit clear (AND NOT) to memory.

Details

Atomic Load-Clear Word atomically loads a 32-bit value from memory, performs a bitwise AND with the complement of Ws (clearing specified bits), stores the result back, and returns the original loaded value in Wt. This is an AArch64-only instruction requiring LSE extension support. No condition flags are affected; this instruction provides release semantics for memory ordering.

Pseudocode Operation

address ← Xn
original_value ← [address]
new_value ← original_value AND NOT(Ws)
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied

Example

LDCLR w6, w3, [x1]

Encoding

Binary Layout
10
111
0
00
0
0
1
Rs
0
001
00
Rn
Rt
 
Format Atomic
Opcode 0xB8201000
Extension LSE (Atomics)

Operands

  • Ws
    Value
  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xB8201000 LDCLR <Ws>, <Wt>, [<Xn|SP>] A64 10 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 0 | 001 | 00 | Rn | Rt
0xF8201000 LDCLR <Xs>, <Xt>, [<Xn|SP>] A64 11 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 0 | 001 | 00 | Rn | Rt

Description

Atomic bit clear on word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(datasize) value;
bits(datasize) data;

AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_BIC, acquire, release, tagchecked);

value = X[s, datasize];
if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

bits(datasize) comparevalue = bits(datasize) UNKNOWN;    // Irrelevant when not executing CAS
data = MemAtomic(address, comparevalue, value, accdesc);

if t != 31 then
    X[t, regsize] = ZeroExtend(data, regsize);