vaba

Vector Absolute Difference and Accumulate

VABA<c>.<dt> <Qd>, <Qn>, <Qm>

Computes absolute difference and adds to accumulator.

Details

NEON Vector Absolute Difference and Accumulate: computes the absolute difference between corresponding elements in Qn and Qm, then adds the results to the corresponding elements in Qd (accumulation). The data type (dt) determined by sz (8, 16, 32 bits) specifies element width. NEON flags (FPSCR) are not modified; no general condition flags are affected.

Pseudocode Operation

for i = 0 to num_elements(Qd, dt) - 1
  diff ← abs(Qn[i] - Qm[i])
  Qd[i] ← Qd[i] + diff

Example

VABA.dt q0, q1, q2

Encoding

Binary Layout
1111001
U
0
D
size
Vn
Vd
0111
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000710
Extension NEON (SIMD)

Operands

  • Qd
    Dest/Acc
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000710 VABA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0111 | N | 0 | M | 1 | Vm
0xF2000750 VABA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0111 | N | 1 | M | 1 | Vm
0xEF000710 VABA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> T32 111 | U | 11110 | D | size | Vn | Vd | 0111 | N | 0 | M | 1 | Vm
0xEF000750 VABA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> T32 111 | U | 11110 | D | size | Vn | Vd | 0111 | N | 1 | M | 1 | Vm

Description

Vector Absolute Difference and Accumulate subtracts the elements of one vector from the corresponding elements of another vector, and accumulates the absolute values of the results into the elements of the destination vector. Operand and result elements are all integers of the same length. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Elem[Din[n+r],e,esize];
            op2 = Elem[Din[m+r],e,esize];
            absdiff = Abs(Int(op1,unsigned) - Int(op2,unsigned));
            if long_destination then
                Elem[Q[d>>1],e,2*esize] = Elem[Qin[d>>1],e,2*esize] + absdiff;
            else
                Elem[D[d+r],e,esize] = Elem[Din[d+r],e,esize] + absdiff;