tbl

Vector Table Lookup

TBL <Vd>.<T>, { <Vn>.16B, ... }, <Vm>.<T>

Look up elements in a table of vectors using indices.

Details

Uses byte-index elements in Vm to look up corresponding bytes in a table formed by one or more consecutive SIMD registers starting at Vn, writing the results to Vd. Out-of-range indices return zero; this is a pure permutation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

Pseudocode Operation

bits(128) table[(len+1)*128-1:0];
for i = 0 to len
  table[i*128 +: 128] ← V[(Rn + i) mod 32];
for e = 0 to elements-1
  index ← Vm[e*8 +: 8];
  if index < (len+1)*16 then
    result[e*8 +: 8] ← table[index*8 +: 8];
  else
    result[e*8 +: 8] ← 0;
Vd ← result;

Example

TBL v0.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
00
0
Rm
0
00
0
00
Rn
Rd
 
Format SIMD Table
Opcode 0x0E000000
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    Table
  • Vm
    Indices

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E000000 TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta> A64 0 | Q | 001110 | 00 | 0 | Rm | 0 | 00 | 0 | 00 | Rn | Rd
0x0E002000 TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta> A64 0 | Q | 001110 | 00 | 0 | Rm | 0 | 01 | 0 | 00 | Rn | Rd
0x0E004000 TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta> A64 0 | Q | 001110 | 00 | 0 | Rm | 0 | 10 | 0 | 00 | Rn | Rd
0x0E006000 TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta> A64 0 | Q | 001110 | 00 | 0 | Rm | 0 | 11 | 0 | 00 | Rn | Rd
0x05203000 TBL <Zd>.<T>, { <Zn>.<T> }, <Zm>.<T> A64 00000101 | size | 1 | Zm | 001100 | Zn | Zd
0x05202800 TBL <Zd>.<T>, { <Zn1>.<T>, <Zn2>.<T> }, <Zm>.<T> A64 00000101 | size | 1 | Zm | 00101 | 0 | Zn | Zd

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) indices = V[m, datasize];
bits(128*regs) table = Zeros(128 * regs);
bits(datasize) result;
integer index;

// Create table from registers
for i = 0 to regs-1
    table<128*i+127:128*i> = V[n, 128];
    n = (n + 1) MOD 32;

result = if is_tbl then Zeros(datasize) else V[d, datasize];
for i = 0 to elements-1
    index = UInt(Elem[indices, i, 8]);
    if index < 16 * regs then
        Elem[result, i, 8] = Elem[table, index, 8];

V[d, datasize] = result;