vdiv

Vector Divide (Double)

VDIV<c>.F64 <Dd>, <Dn>, <Dm>

Divides two double-precision registers.

Details

Divides the 64-bit double-precision value in Dn by the value in Dm and places the floating-point result in Dd. The operation follows IEEE 754 semantics for rounding and exception handling. FPSCR condition flags (N, Z, C, V) may be set based on the result and any exceptions; this instruction is available only in A32 and T32 with VFP support.

Pseudocode Operation

Dd ← FPDiv(Dn, Dm); FPSCR.N ← Dd[63]; FPSCR.Z ← (Dd == 0.0); FPSCR.C ← FPExceptionRaised(); FPSCR.V ← FPInvalidOp();

Example

VDIV.F64 d0, d1, d2

Encoding

Binary Layout
cond
1110
1
D
00
Vn
Vd
10
11
N
0
M
0
Vm
 
Format VFP Arith
Opcode 0x0E800B00
Extension VFP (Float)

Operands

  • Dd
    Destination 64-bit SIMD/FP register
  • Dn
    Dividend
  • Dm
    Divisor

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E800900 VDIV{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0x0E800A00 VDIV{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0x0E800B00 VDIV{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> A32 cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xEE800900 VDIV{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> T32 11101110 | 1 | D | 00 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0xEE800A00 VDIV{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> T32 11101110 | 1 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0xEE800B00 VDIV{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> T32 11101110 | 1 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm

Description

Divide divides one floating-point value by another floating-point value and writes the result to a third floating-point register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    case esize of
        when 16
            S[d] = Zeros(16) : FPDiv(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
        when 32
            S[d] = FPDiv(S[n], S[m], FPSCR[]);
        when 64
            D[d] = FPDiv(D[n], D[m], FPSCR[]);