vdiv

Vector Divide (Double)

VDIV<c>.F64 <Dd>, <Dn>, <Dm>

Divides two double-precision registers.

Details

The Vector Divide instruction divides two double-precision registers.

Pseudocode Operation

Dd ← Dn / Dm
// Quotient truncated toward zero

Example

VDIV.F64 d0, d1, d2

Encoding

Binary Layout
cond
11101000
0
D
Vn
Vd
1011
N
0
M
Vm
 
Format VFP Arith
Opcode 0x0E800B00
Extension VFP (Float)

Operands

  • Dd
    Destination 64-bit SIMD/FP register
  • Dn
    Dividend
  • Dm
    Divisor