and

Bitwise AND (Immediate 64-bit)

AND <Xd|SP>, <Xn>, #<imm>

Bitwise AND with logical immediate (64-bit).

Details

Bitwise AND 64-bit register with a logical immediate. Performs a bitwise AND of Xn with a 64-bit logical immediate, stores the result in Xd. Does not modify condition flags. AArch64-only instruction executing at any privilege level.

Pseudocode Operation

imm_val ← DecodeBitMasks(N, immr, imms, 64)
Xd ← Xn AND imm_val

Example

AND x0, x1, #16

Encoding

Binary Layout
1
00
100100
N
immr
imms
Rn
Rd
 
Format Logical (Immediate)
Opcode 0x92000000
Extension Base

Operands

  • Xd
    Destination 64-bit integer register
  • Xn
    First source / base 64-bit integer register
  • imm
    Logical Imm

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E201C00 AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 00 | 1 | Rm | 00011 | 1 | Rn | Rd
0x12000000 AND <Wd|WSP>, <Wn>, #<imm> A64 0 | 00 | 100100 | 0 | immr | imms | Rn | Rd
0x92000000 AND <Xd|SP>, <Xn>, #<imm> A64 1 | 00 | 100100 | N | immr | imms | Rn | Rd
0x0A000000 AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 00 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x8A000000 AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 00 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x25004000 AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 0 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 0 | Pd
0x041A0000 AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 011 | 01 | 0 | 000 | Pg | Zm | Zdn
0x05800000 AND <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 1 | 0 | 0000 | imm13 | Zdn
0x04203000 AND <Zd>.D, <Zn>.D, <Zm>.D A64 00000100 | 0 | 0 | 1 | Zm | 001100 | Zn | Zd

Description

Bitwise AND (immediate) performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];

result = operand1 AND imm;
if d == 31 then
    SP[] = ZeroExtend(result, 64);
else
    X[d, datasize] = result;