revh

SVE Reverse Halfwords in Elements

REVH <Zd>.<T>, <Pg>/M, <Zn>.<T>

Reverses halfwords within 32/64-bit elements.

Pseudocode Operation

for i = 0 to VL/esize-1
  if Pg[i] then
    case esize of
      32: Zd[i+1:i] ← reverse_halfwords_in_32bit(Zn[i+1:i])
      64: Zd[i+1:i] ← reverse_halfwords_in_64bit(Zn[i+1:i])
  else
    Zd[i+1:i] ← Zd[i+1:i]

Example

REVH z0.s.T, p0/m/M, z1.s.T

Encoding

Binary Layout

00000101

31:24

size

23:22

1001

21:18

100

15:13

12:10

9:5

4:0

Format SVE Permute

Opcode 0x05258000

Extension SVE

Operands

Zd
Destination scalable vector register (SVE)
Pg
Mask
Zn
First source scalable vector register (SVE)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x05258000	REVH <Zd>.<T>, <Pg>/M, <Zn>.<T>		A64		00000101 \| size \| 1001 \| 0 \| 1 \| 100 \| Pg \| Zn \| Zd

Description

Reverse the order of 8-bit bytes, 16-bit halfwords or 32-bit words within each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = Reverse(element, swsize);

Z[d, VL] = result;