vceq

Vector Compare Equal

VCEQ<c>.<dt> <Qd>, <Qn>, <Qm>

Sets destination bits to all 1s if elements equal, else 0s.

Pseudocode Operation

for i = 0 to (128 / element_size) - 1 do
  if Qn[i] == Qm[i] then
    Qd[i] ← all_ones
  else
    Qd[i] ← all_zeros
  end if
end for

Example

VCEQ.dt q0, q1, q2

Encoding

Binary Layout

1111001

31:25

1

24

0

23

D

22

size

21:20

Vn

19:16

Vd

15:12

1000

11:8

N

7

1

6

M

5

1

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF3000850

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qn
  First source 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3B10100	VCEQ{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0		A32		111100111 | D | 11 | size | 01 | Vd | 0 | F | 010 | 0 | M | 0 | Vm
0xF3B10140	VCEQ{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0		A32		111100111 | D | 11 | size | 01 | Vd | 0 | F | 010 | 1 | M | 0 | Vm
0xFFB10100	VCEQ{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0		T32		111111111 | D | 11 | size | 01 | Vd | 0 | F | 010 | 0 | M | 0 | Vm
0xFFB10140	VCEQ{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0		T32		111111111 | D | 11 | size | 01 | Vd | 0 | F | 010 | 1 | M | 0 | Vm
0xF3000810	VCEQ{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		A32		1111001 | 1 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 1 | Vm
0xF3000850	VCEQ{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		A32		1111001 | 1 | 0 | D | size | Vn | Vd | 1000 | N | 1 | M | 1 | Vm
0xF2000E00	VCEQ{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		A32		1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1110 | N | 0 | M | 0 | Vm
0xF2000E40	VCEQ{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		A32		1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1110 | N | 1 | M | 0 | Vm
0xFF000810	VCEQ{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		T32		111 | 1 | 11110 | D | size | Vn | Vd | 1000 | N | 0 | M | 1 | Vm
0xFF000850	VCEQ{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		T32		111 | 1 | 11110 | D | size | Vn | Vd | 1000 | N | 1 | M | 1 | Vm
0xEF000E00	VCEQ{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		T32		111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1110 | N | 0 | M | 0 | Vm
0xEF000E40	VCEQ{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		T32		111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1110 | N | 1 | M | 0 | Vm

Description

Vector Compare Equal takes each element in a vector, and compares it with the corresponding element of a second vector. If they are equal, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros. The operand vector elements are the same type, and are integers or floating-point numbers. The result vector elements are fields the same size as the operand vector elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Elem[D[n+r],e,esize];  op2 = Elem[D[m+r],e,esize];
            boolean test_passed;
            if int_operation then
                test_passed = (op1 == op2);
            else
                test_passed = FPCompareEQ(op1, op2, StandardFPSCRValue());
            Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);