vceq

Vector Compare Equal

VCEQ<c>.<dt> <Qd>, <Qn>, <Qm>

Sets destination bits to all 1s if elements equal, else 0s.

Details

The Vector Compare Equal instruction sets destination bits to all 1s if elements equal, else 0s.

Pseudocode Operation

// Sets destination bits to all 1s if elements equal, else 0s

Example

VCEQ.dt q0, q1, q2

Encoding

Binary Layout
11110010
0
sz
0
Vn
Vd
1000
N
Q
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000810
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register