addp

Scalar Add Pairwise

ADDP <Dd>, <Vn>.<T>

Adds two 64-bit values to a 64-bit result (Scalar NEON).

Details

Adds the two 64-bit elements of a NEON vector register pairwise and stores the scalar 64-bit result in a destination register. Condition flags (N, Z, C, V) are set according to the result. AArch64 only with NEON extension.

Pseudocode Operation

result ← (Vn[0] as i64) + (Vn[1] as i64)
Dd ← result
N ← result[63]
Z ← (result == 0)
C ← Carry_Out(Vn[0], Vn[1])
V ← Overflow_From_Add(Vn[0], Vn[1])

Example

ADDP d0, v1.4s.T

Encoding

Binary Layout

01011110

11110001

101110

Format NEON Scalar

Opcode 0x5E31B800

Extension NEON (Scalar)

Operands

Dd
Destination 64-bit SIMD/FP register
Vn
First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x5EF1B800	ADDP D<d>, <Vn>.2D	A64	01 \| 0 \| 11110 \| 11 \| 11000 \| 11011 \| 10 \| Rn \| Rd
0x0E20BC00	ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>	A64	0 \| Q \| 0 \| 01110 \| size \| 1 \| Rm \| 10111 \| 1 \| Rn \| Rd
0x4411A000	ADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>	A64	01000100 \| size \| 010 \| 0 \| 0 \| 1 \| 101 \| Pg \| Zm \| Zdn

Description

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(128) operand = V[n, 128];
V[d, 64] = IntReduce(ReduceOp_ADD, operand, 64);