ldrex

Load Register Exclusive (A32)

LDREX<c> <Rt>, [<Rn>]

Loads a word and marks physical address as exclusive.

Details

Loads a 32-bit word from memory and tags the physical address as exclusively held by the processor, enabling atomic compare-and-swap sequences via STREX. The address must be word-aligned. Condition flags are not affected. This instruction requires word-aligned addresses and is available in A32 only; it is essential for implementing locks and atomic operations.

Pseudocode Operation

address ← Rn;
if (address MOD 4) != 0 then UNPREDICTABLE;
Rt ← MemRead(address, 4);
MarkExclusive(address, ProcessorID(), 4);

Example

LDREX r3, [r1]

Encoding

Binary Layout
cond
00011
00
1
Rn
Rt
1
1
1
1
1001
1111
 
Format Load/Store
Opcode 0x01900F9F
Extension A32 (Atomic)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01900F9F LDREX{<c>}{<q>} <Rt>, [<Rn> {, {#}<imm>}] A32 cond | 00011 | 00 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111
0xE8500F00 LDREX{<c>}{<q>} <Rt>, [<Rn> {, #<imm>}] T32 11101000010 | 1 | Rn | Rt | 1111 | imm8

Description

Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n] + imm32;
    AArch32.SetExclusiveMonitors(address,4);
    R[t] = MemA[address,4];