ldaprh

Load-Acquire RCpc Register Halfword

LDAPRH <Wt>, [<Xn|SP>]

Loads a halfword with RCpc Acquire semantics.

Details

Load-Acquire RCpc Register Halfword. Loads an unsigned halfword from memory with RCpc (Release Consistent process-consistent) Acquire semantics. Provides a one-way barrier: subsequent memory operations cannot be reordered before this load. The zero-extended halfword is written to Wt. Condition flags are not affected. AArch64-only.

Pseudocode Operation

address ← Xn
data ← ZeroExtend([address], 16)
Wt ← data
AcquireBarrier(RCpc)

Example

LDAPRH w3, [x1]

Encoding

Binary Layout
01
111
0
00
1
0
1
11111
1
100
00
Rn
Rt
 
Format Load/Store
Opcode 0x78BFC000
Extension Base (RCpc)

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x78BFC000 LDAPRH <Wt>, [<Xn|SP> {, #0}] A64 01 | 111 | 0 | 00 | 1 | 0 | 1 | 11111 | 1 | 100 | 00 | Rn | Rt

Description

Load-Acquire RCpc Register Halfword derives an address from a base register value, loads a halfword from the derived address in memory, zero-extends it and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(16) data;

AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

data = Mem[address, 2, accdesc];
X[t, 32] = ZeroExtend(data, 32);