frintm

Floating-Point Round to Integral (Minus Infinity)

FRINTM <Hd|Sd|Dd>, <Hn|Sn|Dn>

Rounds float to integral value towards minus infinity (Floor).

Details

Rounds a floating-point scalar value towards negative infinity (floor). The rounding mode is always "round towards minus infinity" regardless of the FPCR rounding mode setting. This is an AArch64-only instruction that does not modify condition flags.

Pseudocode Operation

rounded_val ← RoundToIntegral_MinusInfinity(Vn)
Vd ← rounded_val

Example

FRINTM Dd, Dn

Encoding

Binary Layout
0
0
0
11110
00
1001
010
10000
Rn
Rd
 
Format FP Data Processing
Opcode 0x1E254000
Extension Floating Point

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x6502A000 FRINTM <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 01100101 | size | 000 | 01 | 0 | 101 | Pg | Zn | Zd
0x0E799800 FRINTM <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 0 | 1111001100 | 1 | 10 | Rn | Rd
0x0E219800 FRINTM <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 0 | sz | 100001100 | 1 | 10 | Rn | Rd
0x1EE54000 FRINTM <Hd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1001 | 010 | 10000 | Rn | Rd
0x1E254000 FRINTM <Sd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 1001 | 010 | 10000 | Rn | Rd
0x1E654000 FRINTM <Dd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 1001 | 010 | 10000 | Rn | Rd
0xC1AAE000 FRINTM { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } A64 11000001 | 1 | 0 | 101 | 01 | 0 | 111000 | Zn | 0 | Zd | 0
0xC1BAE000 FRINTM { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } A64 11000001 | 1 | 0 | 111 | 01 | 0 | 111000 | Zn | 00 | Zd | 00

Description

Floating-point Round to Integral, toward Minus infinity (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);
bits(esize) operand = V[n, esize];

Elem[result, 0, esize] = FPRoundInt(operand, FPCR, rounding, FALSE);

V[d, 128] = result;