push

Push (Thumb)

PUSH <registers>

Push registers to stack (Thumb 16-bit).

Details

Push Registers to Stack stores multiple registers to memory addresses specified by the SP register, decrementing SP before each store. The M bit in the encoding indicates whether the LR is included in the register list. This Thumb 16-bit instruction does not affect condition flags.

Pseudocode Operation

address ← SP
for each register in register_list (in descending order):
  address ← address - 4
  [address] ← register
SP ← address
if M == 1 then
  address ← address - 4
  [address] ← LR
  SP ← address

Example

PUSH registers

Encoding

Binary Layout
1011
0
10
M
register_list
 
Format Thumb Store Multiple
Opcode 0xB400
Extension T32 (Base)

Operands

  • registers
    List

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xB400 PUSH{<c>}{<q>} <registers> T32 1011 | 0 | 10 | M | register_list
0x092D0000 PUSH{<c>}{<q>} <registers> A32 cond | 100 | 1 | 0 | 0 | 1 | 0 | 1101 | register_list
0xE92D0000 PUSH{<c>}.W <registers> T32 1110100 | 10 | 0 | 1 | 0 | 1101 | 0 | M | register_list
0x052D0004 PUSH{<c>}{<q>} <single_register_list> A32 cond | 010 | 1 | 0 | 0 | 1 | 0 | 1101 | Rt | 000000000100
0xF84D0D04 PUSH{<c>}{<q>} <single_register_list> T32 111110000 | 10 | 0 | 1101 | Rt | 1 | 1 | 0 | 1 | 00000100

Description

Push Multiple Registers to Stack stores multiple general-purpose registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also Encoding of lists of general-purpose registers and the PC.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[13] - 4*BitCount(registers);
    for i = 0 to 14
        if registers<i> == '1' then
            if i == 13 && i != LowestSetBit(registers) then  // Only possible for encoding A1
                MemA[address,4] = bits(32) UNKNOWN;
            else
                if UnalignedAllowed then
                    MemU[address,4] = R[i];
                else
                    MemA[address,4] = R[i];
            address = address + 4;
    if registers<15> == '1' then  // Only possible for encoding A1 or A2
        if UnalignedAllowed then
            MemU[address,4] = PCStoreValue();
        else
            MemA[address,4] = PCStoreValue();
    R[13] = R[13] - 4*BitCount(registers);