vdiv

Vector Divide (VFP)

VDIV<c>.F32 <Sd>, <Sn>, <Sm>

Divides two floating-point values.

Details

Divides two single-precision floating-point values (Sn / Sm) and stores the result in Sd. This VFP instruction performs floating-point division on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR; division by zero generates a floating-point exception or returns infinity depending on exception settings. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.

Pseudocode Operation

Sd ← Sn / Sm
FPSCR.NZCV ← FP_CC(result)
if (Sm == 0.0) then FP_Exception(DivideByZero)

Example

VDIV.F32 s0, s1, s2

Encoding

Binary Layout
cond
1110
1
D
00
Vn
Vd
10
10
N
0
M
0
Vm
 
Format VFP Arith
Opcode 0x0E800A00
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sn
    Dividend
  • Sm
    Divisor

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E800900 VDIV{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0x0E800A00 VDIV{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0x0E800B00 VDIV{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> A32 cond | 1110 | 1 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xEE800900 VDIV{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> T32 11101110 | 1 | D | 00 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0xEE800A00 VDIV{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> T32 11101110 | 1 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0xEE800B00 VDIV{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> T32 11101110 | 1 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm

Description

Divide divides one floating-point value by another floating-point value and writes the result to a third floating-point register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    case esize of
        when 16
            S[d] = Zeros(16) : FPDiv(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
        when 32
            S[d] = FPDiv(S[n], S[m], FPSCR[]);
        when 64
            D[d] = FPDiv(D[n], D[m], FPSCR[]);