blx

Branch with Link and Exchange

BLX<c> <Rm>

Calls subroutine and optionally switches to Thumb state.

Pseudocode Operation

LR ← PC + 4
PC ← Rm AND NOT(0x1)
if Rm[0] == 1 then CPSR.T ← 1 else CPSR.T ← 0

Example

BLX r2

Encoding

Binary Layout

cond

31:28

00010010

27:20

1

19

1

18

1

17

1

16

1

15

1

14

1

13

1

12

1

11

1

10

1

9

1

8

0011

7:4

Rm

3:0

 

Format Branch

Opcode 0x012FFF30

Extension A32 (Base)

Operands

• Rm
  Target Reg

Related

More in A32 (Base)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xFA000000	BLX{<c>}{<q>} <label>		A32		1111 | 101 | H | imm24
0xF000C000	BLX{<c>}{<q>} <label>		T32		11110 | S | imm10H | 11 | J1 | 0 | J2 | imm10L | H
0x012FFF30	BLX{<c>}{<q>} <Rm>		A32		cond | 00010010 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0011 | Rm
0x4780	BLX{<c>}{<q>} <Rm>		T32		01000111 | 1 | Rm | 0 | 0 | 0

Description

Branch with Link and Exchange (register) calls a subroutine at an address specified in the register, and if necessary changes to the instruction set indicated by bit[0] of the register value. If the value in bit[0] is 0, the instruction set after the branch will be A32. If the value in bit[0] is 1, the instruction set after the branch will be T32.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    target = R[m];
    bits(32) next_instr_addr;
    if CurrentInstrSet() == InstrSet_A32 then
        next_instr_addr = PC - 4;
        LR = next_instr_addr;
    else
        next_instr_addr = PC - 2;
        LR = next_instr_addr<31:1> : '1';
    BXWritePC(target, BranchType_INDCALL);