sqadd

Vector Signed Saturating Add

SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Adds signed integers with saturation.

Details

The Vector Signed Saturating Add instruction adds signed integers with saturation.

Pseudocode Operation

Vd ← Vn + Vm
// Flags affected: N, Z, C, V

Example

SQADD v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
size
00001
Rm
0000
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E200C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register