sqadd

Vector Signed Saturating Add

SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Adds signed integers with saturation.

Details

Vector Signed Saturating Add adds corresponding signed integer elements from two NEON registers with saturation, placing the sum into the destination register. If overflow occurs, the result is clamped to the maximum or minimum value representable in the element type. This instruction operates element-wise on all vector elements and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to elements_in_vector(Q, size) - 1 do
  sum ← signed_add(Vn[i], Vm[i])
  if overflow then
    Vd[i] ← (Vn[i] < 0) ? INT_MIN(size) : INT_MAX(size)
  else
    Vd[i] ← sum
  end if
end for

Example

SQADD v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
size
1
Rm
00001
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E200C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E200C00 SQADD <V><d>, <V><n>, <V><m> A64 01 | 0 | 11110 | size | 1 | Rm | 00001 | 1 | Rn | Rd
0x0E200C00 SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | size | 1 | Rm | 00001 | 1 | Rn | Rd
0x44188000 SQADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01000100 | size | 011 | 0 | 0 | 0 | 100 | Pg | Zm | Zdn
0x2524C000 SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} A64 00100101 | size | 100 | 10 | 0 | 11 | sh | imm8 | Zdn
0x04201000 SQADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000100 | size | 1 | Zm | 000 | 10 | 0 | Zn | Zd

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d, datasize] = result;