ld64b

Single-copy Atomic 64-byte Load

LD64B <Xt>, [<Xn|SP>]

Loads a 64-byte block of data atomically (Accelerator support).

Pseudocode Operation

address ← Xn|SP; if address<5:0> != 0 then Fault(Alignment); [Xt, Xt+1, ..., Xt+7] ← [address]; // 64 bytes loaded atomically

Example

LD64B x3, [x1]

Encoding

Binary Layout

11

31:30

111

29:27

0

26

00

25:24

0

23

0

22

1

21

11111

20:16

1

15

101

14:12

00

11:10

Rn

9:5

Rt

4:0

 

Format Load/Store

Opcode 0xF83FD000

Extension LSE (Atomics)

Operands

• Xt
  Dest (First of 8 regs)
• Xn
  First source / base 64-bit integer register

Related

More in LSE (Atomics)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF83FD000	LD64B <Xt>, [<Xn|SP> {, #0}]		A64		11 | 111 | 0 | 00 | 0 | 0 | 1 | 11111 | 1 | 101 | 00 | Rn | Rt

Description

Single-copy Atomic 64-byte Load derives an address from a base register value, loads eight 64-bit doublewords from a memory location, and writes them to consecutive registers, Xt to X(t+7). The data that is loaded is atomic and is required to be 64-byte aligned.

Operation

CheckLDST64BEnabled();

bits(512) data;
bits(64) address;
bits(64) value;

AccessDescriptor accdesc = CreateAccDescLS64(memop, tagchecked);
if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

data = MemLoad64B(address, accdesc);

for i = 0 to 7
    value = data<63+64*i:64*i>;
    if BigEndian(accdesc.acctype) then value = BigEndianReverse(value);
    X[t+i, 64] = value;