zip2

SVE Zip 2

ZIP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

Interleaves elements from the upper halves.

Details

Interleaves elements from the upper halves of two SVE vectors, placing odd-indexed elements from the upper half of Zn and even-indexed elements from the upper half of Zm into alternating positions in Zd. This is a data-permutation instruction that does not modify condition flags. Execution is restricted to AArch64 with the SVE extension enabled.

Pseudocode Operation

half ← VL / (2 * esize)
for i = 0 to VL/esize-1 step 2
  Zd[i, esize] ← Zn[half + i/2, esize]
  Zd[i+1, esize] ← Zm[half + i/2, esize]

Example

ZIP2 z0.s.T, z1.s.T, z2.s.T

Encoding

Binary Layout

00000101

size

011

Format SVE Permute

Opcode 0x05206400

Extension SVE

Operands

Zd
Destination scalable vector register (SVE)
Zn
First source scalable vector register (SVE)
Zm
Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x05204400	ZIP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>	A64	00000101 \| size \| 10 \| Pm \| 010 \| 0 \| 0 \| 1 \| 0 \| Pn \| 0 \| Pd
0x05206400	ZIP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>	A64	00000101 \| size \| 1 \| Zm \| 011 \| 00 \| 1 \| Zn \| Zd
0x05A00400	ZIP2 <Zd>.Q, <Zn>.Q, <Zm>.Q	A64	00000101101 \| Zm \| 000 \| 0 \| 0 \| 1 \| Zn \| Zd
0x0E007800	ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>	A64	0 \| Q \| 001110 \| size \| 0 \| Rm \| 0 \| 1 \| 1110 \| Rn \| Rd

Description

Interleave alternating elements from the lowest or highest halves of the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated. The 128-bit element variant requires that the Effective SVE vector length is at least 256 bits. ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
if VL < esize * 2 then UNDEFINED;
constant integer pairs = VL DIV (esize * 2);
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result = Zeros(VL);

integer base = part * pairs;
for p = 0 to pairs-1
    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];

Z[d, VL] = result;