ldg

Load Allocation Tag

LDG <Xt>, [<Xn|SP>, #<simm>]

Loads the Allocation Tag from memory.

Pseudocode Operation

address ← Xn + (simm << 4)  // simm is a signed 9-bit value, scaled by 16
memory_tag ← load_tag_from_memory(address)
Xt ← (memory_tag << 56) & 0xF000000000000000

Example

LDG x3, [x1, #-8]

Encoding

Binary Layout

11011001

31:24

23:22

imm9

20:12

11:10

9:5

4:0

Format Load/Store

Opcode 0xD9600000

Extension MTE (Memory Tagging)

Operands

Xt
Transfer 64-bit integer register (load/store)
Xn
First source / base 64-bit integer register
simm
Signed immediate offset

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xD9600000	LDG <Xt>, [<Xn\|SP>{, #<simm>}]		A64		11011001 \| 01 \| 1 \| imm9 \| 00 \| Xn \| Xt

Description

Load Allocation Tag loads an Allocation Tag from a memory address, generates a Logical Address Tag from the Allocation Tag and merges it into the destination register. The address used for the load is calculated from the base register and an immediate signed offset scaled by the Tag granule.

Operation

bits(64) address;
bits(4) tag;

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

AccessDescriptor accdesc = CreateAccDescLDGSTG(MemOp_LOAD, FALSE);

address = GenerateAddress(address, offset, accdesc);
address = Align(address, TAG_GRANULE);

tag = AArch64.MemTag[address, accdesc];
X[t, 64] = AArch64.AddressWithAllocationTag(X[t, 64], tag);

ldg