lsl

Logical Shift Left (A32)

LSL{S}<c> <Rd>, <Rm>, <Rs>

Shifts a register left.

Details

Shifts the value in Rm left by the number of bits specified in the low 8 bits of Rs, storing the result in Rd. If S=1, the condition flags N, Z, C, and V are updated: N and Z reflect the result, C receives the last bit shifted out, and V is unaffected. Execution is conditional based on the 4-bit condition code; available in A32 only.

Pseudocode Operation

shift_amount ← Rs[7:0];
if shift_amount == 0 then result ← Rm else if shift_amount < 32 then (C_out, result) ← Rm << shift_amount else if shift_amount == 32 then (C_out, result) ← (Rm[31], 0) else (C_out, result) ← (0, 0);
Rd ← result;
if S == 1 then N ← result[31]; Z ← (result == 0); C ← C_out;

Example

LSL r0, r2, r6

Encoding

Binary Layout
cond
00011
01
0
0000
Rd
Rs
0
00
1
Rm
 
Format Data Proc
Opcode 0x01A00010
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register
  • Rs
    Shift amount general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01A00000 LSL{<c>}{<q>} {<Rd>,} <Rm>, #<imm> A32 cond | 00011 | 01 | 0 | 0000 | Rd | imm5 | 00 | 0 | Rm
0x0000 LSL<c>{<q>} {<Rd>,} <Rm>, #<imm> T32 000 | 00 | imm5 | Rm | Rd
0xEA4F0000 LSL<c>.W {<Rd>,} <Rm>, #<imm> T32 1110101 | 0010 | 0 | 1111 | 0 | imm3 | Rd | imm2 | 00 | Rm
0x01A00010 LSL{<c>}{<q>} {<Rd>,} <Rm>, <Rs> A32 cond | 00011 | 01 | 0 | 0000 | Rd | Rs | 0 | 00 | 1 | Rm
0x4080 LSL<c>{<q>} {<Rdm>,} <Rdm>, <Rs> T32 010000 | 0010 | Rs | Rdm
0xFA00F000 LSL<c>.W {<Rd>,} <Rm>, <Rs> T32 111110100 | 00 | 0 | Rm | 1111 | Rd | 0000 | Rs

Description

shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register