lsl

Logical Shift Left (A32)

LSL{S}<c> <Rd>, <Rm>, <Rs>

Shifts a register left.

Pseudocode Operation

shift_amount ← Rs[7:0];
if shift_amount == 0 then result ← Rm else if shift_amount < 32 then (C_out, result) ← Rm << shift_amount else if shift_amount == 32 then (C_out, result) ← (Rm[31], 0) else (C_out, result) ← (0, 0);
Rd ← result;
if S == 1 then N ← result[31]; Z ← (result == 0); C ← C_out;

Example

LSL r0, r2, r6

Encoding

Binary Layout

cond

31:28

00011

27:23

22:21

0000

19:16

15:12

11:8

6:5

3:0

Format Data Proc

Opcode 0x01A00010

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Rm
Second source / offset general-purpose register
Rs
Shift amount general-purpose register

Other forms of lsl

lsl Logical Shift Left (Register)
lsl SVE Shift Left (Predicated)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x01A00000	LSL{<c>}{<q>} {<Rd>,} <Rm>, #<imm>	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| imm5 \| 00 \| 0 \| Rm
0x0000	LSL<c>{<q>} {<Rd>,} <Rm>, #<imm>	T32	000 \| 00 \| imm5 \| Rm \| Rd
0xEA4F0000	LSL<c>.W {<Rd>,} <Rm>, #<imm>	T32	1110101 \| 0010 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm2 \| 00 \| Rm
0x01A00010	LSL{<c>}{<q>} {<Rd>,} <Rm>, <Rs>	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| Rs \| 0 \| 00 \| 1 \| Rm
0x4080	LSL<c>{<q>} {<Rdm>,} <Rdm>, <Rs>	T32	010000 \| 0010 \| Rs \| Rdm
0xFA00F000	LSL<c>.W {<Rd>,} <Rm>, <Rs>	T32	111110100 \| 00 \| 0 \| Rm \| 1111 \| Rd \| 0000 \| Rs

Description

Shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register

lsl