dup

Duplicate Vector Element (Element)

DUP <Vd>.<T>, <Vn>.<Ts>[<index>]

Duplicates a vector element to all elements in destination.

Details

Duplicates a single element from a vector and replicates it to fill all elements in the destination vector. The element index is encoded in the imm5 field, which also determines the element size based on the position of the most significant set bit. This is a NEON SIMD instruction available in AArch64 only, with Q determining 64-bit (Q=0) or 128-bit (Q=1) operation. No condition flags are affected.

Pseudocode Operation

element_size ← decode_element_size(imm5);
element ← Vn.<element_size>[index_from_imm5];
for i = 0 to (vector_length / element_size - 1)
  Vd.<element_size>[i] ← element;

Example

DUP v0.4s.T, v1.4s.Ts[index]

Encoding

Binary Layout
0
Q
0
01110000
imm5
0
0000
1
Rn
Rd
 
Format SIMD Copy
Opcode 0x0E000400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    Src Vector
  • index
    Index

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E000400 DUP <V><d>, <Vn>.<T>[<index>] A64 01 | 0 | 11110000 | imm5 | 0 | 0000 | 1 | Rn | Rd
0x0E000400 DUP <Vd>.<T>, <Vn>.<Ts>[<index>] A64 0 | Q | 0 | 01110000 | imm5 | 0 | 0000 | 1 | Rn | Rd
0x0E000C00 DUP <Vd>.<T>, <R><n> A64 0 | Q | 0 | 01110000 | imm5 | 0 | 0001 | 1 | Rn | Rd
0x2538C000 DUP <Zd>.<T>, #<imm>{, <shift>} A64 00100101 | size | 111 | 0 | 0 | 011 | sh | imm8 | Zd
0x05203800 DUP <Zd>.<T>, <R><n|SP> A64 00000101 | size | 100000001110 | Rn | Zd
0x05202000 DUP <Zd>.<T>, <Zn>.<T>[<imm>] A64 00000101 | imm2 | 1 | tsz | 001000 | Zn | Zd

Description

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(idxdsize) operand = V[n, idxdsize];
bits(datasize) result;
bits(esize) element;

element = Elem[operand, index, esize];
for e = 0 to elements-1
    Elem[result, e, esize] = element;
V[d, datasize] = result;