uxth

Unsigned Extend Halfword (Thumb)

UXTH <Rd>, <Rm>

Zero-extends halfword to word (Thumb).

Details

Zero-extends a 16-bit halfword value to a 32-bit word in the T32 (Thumb) instruction set. The least-significant halfword of Rm is zero-extended and written to Rd. No condition flags are affected.

Pseudocode Operation

Rd = ZeroExtend(Rm[15:0], 32)

Example

UXTH r0, r2

Encoding

Binary Layout
10110010
1
0
Rm
Rd
 
Format Thumb Data Proc
Opcode 0xB280
Extension T32 (Thumb)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06FF0070 UXTH{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>} A32 cond | 01101 | 1 | 11 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm
0xB280 UXTH{<c>}{<q>} {<Rd>,} <Rm> T32 10110010 | 1 | 0 | Rm | Rd
0xFA1FF080 UXTH{<c>}.W {<Rd>,} <Rm> T32 111110100 | 00 | 1 | 1111 | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = ZeroExtend(rotated<15:0>, 32);