cpy

SVE Copy (Predicated)

CPY <Zd>.<T>, <Pg>/M, <R><n>

Copies scalar value to active vector elements (Alias for DUP predicated).

Details

Copies a scalar value from a general-purpose register to active elements of a vector under predicate control. Only elements where the predicate is true are updated; inactive elements remain unchanged. Operates on elements of type T and no flags are affected. This is an AArch64-only SVE instruction.

Pseudocode Operation

for i = 0 to VL/esize-1
  if Pg[i] then
    Zd[i] ← Rn

Example

CPY z0.s.T, p0/m/M, Rn

Encoding

Binary Layout
00000101
size
100000100
Pg
Vn
Zd
 
Format SVE Move
Opcode 0x05208000
Extension SVE

Operands

  • Zd
    Destination scalable vector register (SVE)
  • Pg
    Mask
  • Rn
    First source / base general-purpose register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x05100000 CPY <Zd>.<T>, <Pg>/Z, #<imm>{, <shift>} A64 00000101 | size | 01 | Pg | 0 | 0 | sh | imm8 | Zd
0x05104000 CPY <Zd>.<T>, <Pg>/M, #<imm>{, <shift>} A64 00000101 | size | 01 | Pg | 0 | 1 | sh | imm8 | Zd
0x0528A000 CPY <Zd>.<T>, <Pg>/M, <R><n|SP> A64 00000101 | size | 101000101 | Pg | Rn | Zd
0x05208000 CPY <Zd>.<T>, <Pg>/M, <V><n> A64 00000101 | size | 100000100 | Pg | Vn | Zd

Description

Copy the SIMD & floating-point scalar source register to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(esize) operand1 = if AnyActiveElement(mask, esize) then V[n, esize] else Zeros(esize);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        Elem[result, e, esize] = operand1;

Z[d, VL] = result;