asr

Arithmetic Shift Right (A32)

ASR{S}<c> <Rd>, <Rm>, <Rs>

Arithmetic right shift (sign-extending).

Details

Performs an arithmetic right shift of Rm by the number of bits specified in Rs (register shift amount), sign-extending the vacated bits from the left. If the S suffix is present, condition flags are updated: N and Z based on the result, C set to the last bit shifted out, and V is unaffected. Executes in A32 only.

Pseudocode Operation

shift_amount ← Rs[7:0]
if shift_amount == 0 then
  result ← Rm
  carry_out ← C
else if shift_amount < 32 then
  result ← Rm >> shift_amount (arithmetic, sign-extended)
  carry_out ← Rm[shift_amount - 1]
else
  result ← (Rm[31] repeated 32 times)
  carry_out ← Rm[31]
Rd ← result
if S == 1 then
  N ← result[31]
  Z ← (result == 0)
  C ← carry_out
else
  condition_flags unchanged

Example

ASR r0, r2, r6

Encoding

Binary Layout

cond

00011

0000

Format Data Proc

Opcode 0x01A00050

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Rm
Second source / offset general-purpose register
Rs
Shift Amount

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x01A00040	ASR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| imm5 \| 10 \| 0 \| Rm
0x1000	ASR<c>{<q>} {<Rd>,} <Rm>, #<imm>	T32	000 \| 10 \| imm5 \| Rm \| Rd
0xEA4F0020	ASR<c>.W {<Rd>,} <Rm>, #<imm>	T32	1110101 \| 0010 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm2 \| 10 \| Rm
0x01A00050	ASR{<c>}{<q>} {<Rd>,} <Rm>, <Rs>	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| Rs \| 0 \| 10 \| 1 \| Rm
0x4100	ASR<c>{<q>} {<Rdm>,} <Rdm>, <Rs>	T32	010000 \| 0100 \| Rs \| Rdm
0xFA40F000	ASR<c>.W {<Rd>,} <Rm>, <Rs>	T32	111110100 \| 10 \| 0 \| Rm \| 1111 \| Rd \| 0000 \| Rs

Description

shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register