mrs

Move Special Register to Register (Thumb)

MRS <Rd>, <spec_reg>

Read special register (Thumb).

Details

Move Special Register to Register reads the value of a system register specified by spec_reg and writes it to the general-purpose register Rd. In T32/Thumb, this is a 32-bit instruction that accesses APSR, IPSR, EPSR, IAPSR, EAPSR, IEPSR, MSPLIM, PSPLIM, or other banked registers depending on the spec_reg encoding. The instruction does not modify the condition flags; it simply transfers the register value.

Pseudocode Operation

Rd ← ReadSystemReg(spec_reg)

Example

MRS r0, nzcv

Encoding

Binary Layout
11110011111
R
1
1
1
1
10
0
0
Rd
0
0
0
0
0
0
0
0
 
Format Thumb System
Opcode 0xF3EF8000
Extension A32 (System)

Operands

  • Rd
    Destination general-purpose register
  • spec_reg
    Reg

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x010F0000 MRS{<c>}{<q>} <Rd>, <spec_reg> A32 cond | 00010 | R | 0 | 0 | 1111 | Rd | 0 | 0 | 0 | 0 | 0000 | 0000
0xF3EF8000 MRS{<c>}{<q>} <Rd>, <spec_reg> T32 11110011111 | R | 1 | 1 | 1 | 1 | 10 | 0 | 0 | Rd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0x01000200 MRS{<c>}{<q>} <Rd>, <banked_reg> A32 cond | 00010 | R | 0 | 0 | M1 | Rd | 0 | 0 | 1 | M | 0000 | 0000
0xF3E08020 MRS{<c>}{<q>} <Rd>, <banked_reg> T32 11110011111 | R | M1 | 10 | 0 | 0 | Rd | 0 | 0 | 1 | M | 0 | 0 | 0 | 0

Description

Move Special register to general-purpose register moves the value of the APSR, CPSR, or SPSR_<current_mode> into a general-purpose register. Arm recommends the APSR form when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see APSR. An MRS that accesses the SPSRs is unpredictable if executed in User mode or System mode. An MRS that is executed in User mode and accesses the CPSR returns an unknown value for the CPSR.{E, A, I, F, M} fields.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    if read_spsr then
        if PSTATE.M IN {M32_User,M32_System} then
            UNPREDICTABLE;
        else
            R[d] = SPSR[];
    else
        // CPSR has same bit assignments as SPSR, but with the IT, J, SS, IL, and T bits masked out.
        bits(32) mask = '11111000 11101111 00000011 11011111';
        psr_val = GetPSRFromPSTATE(AArch32_NonDebugState, 32) AND mask;
        if PSTATE.EL == EL0 then
            // If accessed from User mode return UNKNOWN values for E, A, I, F bits, bits<9:6>,
            // and for the M field, bits<4:0>
            psr_val<22> = bits(1) UNKNOWN;
            psr_val<9:6> = bits(4) UNKNOWN;
            psr_val<4:0> = bits(5) UNKNOWN;
        R[d] = psr_val;