esb

Error Synchronization Barrier

ESB

Synchronizes unrecoverable system errors.

Details

Error Synchronization Barrier synchronizes unrecoverable system errors by ensuring that all error conditions are visible to the PE before proceeding. This is a system-level instruction that provides a point of synchronization for RAS (Reliability, Availability, Serviceability) error handling. No condition flags are affected. AArch64-only; requires EL1 or higher privilege.

Pseudocode Operation

SynchronizeErrors()

Example

ESB

Encoding

Binary Layout

11010101000000110010

0010

000

11111

Format System Alias

Opcode 0xD503221F

Extension RAS (Reliability)

Operands

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xD503221F	ESB		A64		11010101000000110010 \| 0010 \| 000 \| 11111

Description

Error Synchronization Barrier is an error synchronization event that might also update DISR_EL1 and VDISR_EL2. This instruction can be used at all Exception levels and in Debug state. In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. See Error Synchronization Barrier in the Arm(R) Reliability, Availability, and Serviceability (RAS) Specification, Armv8, for Armv8-A architecture profile. If the RAS Extension is not implemented, this instruction executes as a NOP.

Operation

if IsFeatureImplemented(FEAT_TME) && TSTATE.depth > 0 then
    FailTransaction(TMFailure_ERR, FALSE);
SynchronizeErrors();
AArch64.ESBOperation();
if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then AArch64.vESBOperation();
TakeUnmaskedSErrorInterrupts();