ldrexb

Load Register Exclusive Byte (A32)

LDREXB<c> <Rt>, [<Rn>]

Loads a byte and marks address as exclusive.

Details

Loads a byte from memory into a register and marks the address as exclusive for synchronization. The byte is zero-extended to 32 bits in the destination register. No condition flags are modified. This is an A32-only instruction that atomically acquires an exclusive lock on the target byte address; the lock is released by a matching STREXB or other exclusive store.

Pseudocode Operation

if ConditionPassed(cond) then
  address ← Rn
  Rt ← ZeroExtend([address], 8)
  SetExclusiveMonitor(address, 1)

Example

LDREXB r3, [r1]

Encoding

Binary Layout
cond
00011
10
1
Rn
Rt
1
1
1
1
1001
1111
 
Format Load/Store Excl
Opcode 0x01D00F9F
Extension A32 (Atomic)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01D00F9F LDREXB{<c>}{<q>} <Rt>, [<Rn>] A32 cond | 00011 | 10 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111
0xE8D00F4F LDREXB{<c>}{<q>} <Rt>, [<Rn>] T32 11101000110 | 1 | Rn | Rt | 1111 | 01 | 00 | 1111

Description

Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    AArch32.SetExclusiveMonitors(address,1);
    R[t] = ZeroExtend(MemA[address,1], 32);