vqshlu

Vector Saturating Shift Left Unsigned

VQSHLU<c>.<dt> <Qd>, <Qm>, #<imm>

Shifts signed elements left, saturating to unsigned result.

Details

Vector Saturating Shift Left Unsigned shifts each signed element in Qm left by an immediate value and saturates the result to an unsigned range. Elements that overflow are clamped to the maximum unsigned value of the result type. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.

Pseudocode Operation

shift_amount ← imm6
for i = 0 to elements-1 do
  result ← SatQ(Qm[i] << shift_amount, 0, max_unsigned_value)
  Qd[i] ← result

Example

VQSHLU.dt q0, q2, #16

Encoding

Binary Layout
1111001
1
1
D
imm6
Vd
011
0
L
1
M
1
Vm
 
Format NEON Shift
Opcode 0xF3800650
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3800610 VQSHLU{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm> A32 1111001 | 1 | 1 | D | imm6 | Vd | 011 | 0 | L | 0 | M | 1 | Vm
0xF3800650 VQSHLU{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm> A32 1111001 | 1 | 1 | D | imm6 | Vd | 011 | 0 | L | 1 | M | 1 | Vm
0xFF800610 VQSHLU{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm> T32 111 | 1 | 11111 | D | imm6 | Vd | 011 | 0 | L | 0 | M | 1 | Vm
0xFF800650 VQSHLU{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm> T32 111 | 1 | 11111 | D | imm6 | Vd | 011 | 0 | L | 1 | M | 1 | Vm

Description

Vector Saturating Shift Left (immediate) takes each element in a vector of integers, left shifts them by an immediate value, and places the results in a second vector. The operand elements must all be the same size, and can be any one of: The result elements are the same size as the operand elements. If the operand elements are signed, the results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            operand = Int(Elem[D[m+r],e,esize], src_unsigned);
            (result, sat) = SatQ(operand << shift_amount, esize, dest_unsigned);
            Elem[D[d+r],e,esize] = result;
            if sat then FPSCR.QC = '1';