ldr

Load Register (Register)

LDR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Loads a word from memory (Register offset).

Pseudocode Operation

offset ← extended_value(Rm, extend_type, shift_amount); address ← Xn + offset; Wt ← [address]

Example

LDR w3, [x1, Rm ]

Encoding

Binary Layout
10
31:30
111
29:27
0
26
00
25:24
01
23:22
1
21
Rm
20:16
option
15:13
S
12
10
11:10
Rn
9:5
Rt
4:0
 
Format Load/Store Reg
Opcode 0xB8600800
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • Rm
    Offset Reg

Related

Other forms of ldr

  • ldr Load SIMD&FP Register (Immediate)
  • ldr Load Register (Immediate)
  • ldr Load Register (Literal)
  • ldr Load Register PC-Relative (A32)
  • ldr Load Register PC-Relative (Thumb)
  • ldr Load Register (A32 Immediate)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x3C400400 LDR <Bt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x7C400400 LDR <Ht>, [<Xn|SP>], #<simm> A64 01 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0xBC400400 LDR <St>, [<Xn|SP>], #<simm> A64 10 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0xFC400400 LDR <Dt>, [<Xn|SP>], #<simm> A64 11 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x3CC00400 LDR <Qt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 11 | 0 | imm9 | 01 | Rn | Rt
0x3C400C00 LDR <Bt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x7C400C00 LDR <Ht>, [<Xn|SP>, #<simm>]! A64 01 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0xBC400C00 LDR <St>, [<Xn|SP>, #<simm>]! A64 10 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0xFC400C00 LDR <Dt>, [<Xn|SP>, #<simm>]! A64 11 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x3CC00C00 LDR <Qt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 11 | 0 | imm9 | 11 | Rn | Rt
0x3D400000 LDR <Bt>, [<Xn|SP>{, #<pimm>}] A64 00 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0x7D400000 LDR <Ht>, [<Xn|SP>{, #<pimm>}] A64 01 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0xBD400000 LDR <St>, [<Xn|SP>{, #<pimm>}] A64 10 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0xFD400000 LDR <Dt>, [<Xn|SP>{, #<pimm>}] A64 11 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt

Description

Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted and extended. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) offset = ExtendReg(m, extend_type, shift, 64);
bits(64) address;
bits(datasize) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, TRUE);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = Mem[address, datasize DIV 8, accdesc];
X[t, regsize] = ZeroExtend(data, regsize);