fcmp

Floating-Point Compare (Scalar)

FCMP <Hn|Sn|Dn>, <Hm|Sm|Dm|#0.0>

Compares two floating-point values and updates process flags (NZCV).

Pseudocode Operation

result ← FPCompare(Vn, Vm)
N ← result.N
Z ← result.Z
C ← result.C
V ← result.V

Example

FCMP Dn, Dm|#0.0

Encoding

Binary Layout

0

31

0

30

0

29

11110

28:24

00

23:22

1

21

Rm

20:16

00

15:14

1000

13:10

Rn

9:5

00

4:3

000

2:0

 

Format FP Compare

Opcode 0x1E202000

Extension Floating Point

Operands

• Hn|Sn|Dn
  First source SIMD&FP register (half, single or double-precision)
• Hm|Sm|Dm|0.0
  Second source SIMD/FP vector register

Related

Other forms of fcmp

• fcmp Floating-point Compare (Single)
• fcmp Floating-point Compare (Double)

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x1EE02000	FCMP <Hn>, <Hm>		A64		0 | 0 | 0 | 11110 | 11 | 1 | Rm | 00 | 1000 | Rn | 00 | 000
0x1EE02008	FCMP <Hn>, #0.0		A64		0 | 0 | 0 | 11110 | 11 | 1 | 00000 | 00 | 1000 | Rn | 01 | 000
0x1E202000	FCMP <Sn>, <Sm>		A64		0 | 0 | 0 | 11110 | 00 | 1 | Rm | 00 | 1000 | Rn | 00 | 000
0x1E202008	FCMP <Sn>, #0.0		A64		0 | 0 | 0 | 11110 | 00 | 1 | 00000 | 00 | 1000 | Rn | 01 | 000
0x1E602000	FCMP <Dn>, <Dm>		A64		0 | 0 | 0 | 11110 | 01 | 1 | Rm | 00 | 1000 | Rn | 00 | 000
0x1E602008	FCMP <Dn>, #0.0		A64		0 | 0 | 0 | 11110 | 01 | 1 | 00000 | 00 | 1000 | Rn | 01 | 000

Description

Floating-point quiet Compare (scalar). This instruction compares the two SIMD&FP source register values, or the first SIMD&FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags. This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2;

operand2 = if cmp_with_zero then FPZero('0', datasize) else V[m, datasize];

PSTATE.<N,Z,C,V> = FPCompare(operand1, operand2, signal_all_nans, FPCR);