orr

Logical OR (A32)

ORR{S}<c> <Rd>, <Rn>, <Operand2>

Performs bitwise OR.

Pseudocode Operation

result ← Rn | Operand2
Rd ← result
if S == 1 then
  N ← result[31]
  Z ← (result == 0)
  C ← shifter_carry_out
endif

Example

ORR r0, r1, r2

Encoding

Binary Layout

cond

31:28

00111

27:23

22:21

19:16

15:12

imm12

11:0

Format Data Proc

Opcode 0x03800000

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Rn
First source / base general-purpose register
Operand2
Flexible second operand (register or shifted register)

Other forms of orr

orr Bitwise OR (Immediate)
orr Bitwise OR (Shifted Register)
orr Vector Bitwise OR
orr SVE Bitwise OR (Predicated)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x03800000	ORR{<c>}{<q>} {<Rd>,} <Rn>, #<const>	A32	cond \| 00111 \| 00 \| 0 \| Rn \| Rd \| imm12
0xF0400000	ORR{<c>}{<q>} {<Rd>,} <Rn>, #<const>	T32	11110 \| i \| 0 \| 0010 \| 0 \| Rn \| 0 \| imm3 \| Rd \| imm8
0x01800060	ORR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX	A32	cond \| 00011 \| 00 \| 0 \| Rn \| Rd \| 00000 \| 11 \| 0 \| Rm
0x01800000	ORR{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}	A32	cond \| 00011 \| 00 \| 0 \| Rn \| Rd \| imm5 \| stype \| 0 \| Rm
0x4300	ORR<c>{<q>} {<Rdn>,} <Rdn>, <Rm>	T32	010000 \| 1100 \| Rm \| Rdn
0xEA400030	ORR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX	T32	1110101 \| 0010 \| 0 \| Rn \| 0 \| 000 \| Rd \| 00 \| 11 \| Rm
0xEA400000	ORR<c>.W {<Rd>,} <Rn>, <Rm>	T32	1110101 \| 0010 \| 0 \| Rn \| 0 \| imm3 \| Rd \| imm2 \| stype \| Rm
0x01800010	ORR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs>	A32	cond \| 00011 \| 00 \| 0 \| Rn \| Rd \| Rs \| 0 \| stype \| 1 \| Rm

Description

Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. If the destination register is not the PC, the ORRS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    result = R[n] OR imm32;
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged

orr