sbfx

Signed Bit Field Extract (Thumb)

SBFX <Rd>, <Rn>, #<lsb>, #<width>

Extracts and sign-extends bits.

Pseudocode Operation

lsb_val ← ZeroExtend(imm3:imm2, 6)
width_val ← ZeroExtend(width, 5)
msb ← lsb_val + width_val - 1
extracted ← (Rn >> lsb_val)[width_val-1:0]
if extracted[width_val-1] == 1 then
  Rd ← SignExtend(extracted, 32)
else
  Rd ← ZeroExtend(extracted, 32)

Example

SBFX r0, r1, #0, #width

Encoding

Binary Layout

11110

31:27

0

26

11

25:24

01

23:22

0

21

0

20

Rn

19:16

0

15

imm3

14:12

Rd

11:8

imm2

7:6

0

5

widthm1

4:0

 

Format Thumb Bitfield

Opcode 0xF3400000

Extension A32 (Base)

Operands

• Rd
  Destination general-purpose register
• Rn
  First source / base general-purpose register

Related

Other forms of sbfx

• sbfx Signed Bit Field Extract (A32)

More in A32 (Base)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x07A00050	SBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width>		A32		cond | 01111 | 0 | 1 | widthm1 | Rd | lsb | 101 | Rn
0xF3400000	SBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width>		T32		11110 | 0 | 11 | 01 | 0 | 0 | Rn | 0 | imm3 | Rd | imm2 | 0 | widthm1

Description

Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    R[d] = SignExtend(R[n]<msbit:lsbit>, 32);