ldrexd

Load Register Exclusive Double (A32)

LDREXD<c> <Rt>, <Rt2>, [<Rn>]

Loads a doubleword and marks address as exclusive.

Pseudocode Operation

address ← Rn; value ← MemU[address, 8]; Rt ← value[31:0]; Rt2 ← value[63:32]; ExclusiveMonitorsMarkExclusive(address, ProcessorID(), 8);

Example

LDREXD r3, r4, [r1]

Encoding

Binary Layout

cond

31:28

00011

27:23

01

22:21

1

20

Rn

19:16

Rt

15:12

1

11

1

10

1

9

1

8

1001

7:4

1111

3:0

 

Format Load/Store Excl

Opcode 0x01B00F9F

Extension A32 (Atomic)

Operands

• Rt
  Dest 1
• Rt2
  Dest 2
• Rn
  First source / base general-purpose register

Related

More in A32 (Atomic)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x01B00F9F	LDREXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]		A32		cond | 00011 | 01 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111
0xE8D0007F	LDREXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]		T32		11101000110 | 1 | Rn | Rt | Rt2 | 01 | 11 | 1111

Description

Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    AArch32.SetExclusiveMonitors(address,8);
    value = MemA[address,8];

    // Extract words from 64-bit loaded value such that R[t] is
    // loaded from address and R[t2] from address+4.
    R[t]  = if BigEndian(AccessType_GPR) then value<63:32> else value<31:0>;
    R[t2] = if BigEndian(AccessType_GPR) then value<31:0> else value<63:32>;