rev16

Reverse Bytes in Halfwords (Thumb)

REV16 <Rd>, <Rm>

Reverses bytes in each 16-bit halfword.

Details

Reverses the byte order within each 16-bit halfword independently (bits [31:24] swap with [23:16] and bits [15:8] swap with [7:0]). No condition flags are affected. This is a 32-bit Thumb instruction available in ARMv6 and later.

Pseudocode Operation

Rd[31:24] ← Rm[23:16]
Rd[23:16] ← Rm[31:24]
Rd[15:8] ← Rm[7:0]
Rd[7:0] ← Rm[15:8]

Example

REV16 r0, r2

Encoding

Binary Layout
111110101
001
Rn
1111
Rd
10
01
Rm
 
Format Thumb Misc
Opcode 0xFA90F090
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06BF0FB0 REV16{<c>}{<q>} <Rd>, <Rm> A32 cond | 01101 | 0 | 11 | 1 | 1 | 1 | 1 | Rd | 1 | 1 | 1 | 1 | 1 | 011 | Rm
0xBA40 REV16{<c>}{<q>} <Rd>, <Rm> T32 10111010 | 01 | Rm | Rd
0xFA90F090 REV16{<c>}.W <Rd>, <Rm> T32 111110101 | 001 | Rn | 1111 | Rd | 10 | 01 | Rm

Description

Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    bits(32) result;
    result<31:24> = R[m]<23:16>;
    result<23:16> = R[m]<31:24>;
    result<15:8>  = R[m]<7:0>;
    result<7:0>   = R[m]<15:8>;
    R[d] = result;