add
Vector Add (Integer)
ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
Adds corresponding elements in two vectors.
Details
Adds corresponding integer elements in two NEON vectors and writes the results to the destination vector. Operates element-wise on 8-bit, 16-bit, 32-bit, or 64-bit elements as determined by the size and Q fields. Condition flags (N, Z, C, V) are not affected; wrapping addition is performed on overflow.
Pseudocode Operation
for i = 0 to elements_in_vector - 1
Vd[i] ← Vn[i] + Vm[i]Example
ADD v0.4s.T, v1.4s.T, v2.4s.T
Encoding
Binary Layout
0
Q
0
01110
size
1
Rm
10000
1
Rn
Rd
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0B200000 | ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} | A64 | 0 | 0 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd | ||
| 0x8B200000 | ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}} | A64 | 1 | 0 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd | ||
| 0x11000000 | ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>} | A64 | 0 | 0 | 0 | 100010 | sh | imm12 | Rn | Rd | ||
| 0x91000000 | ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>} | A64 | 1 | 0 | 0 | 100010 | sh | imm12 | Rn | Rd | ||
| 0x0B000000 | ADD <Wd>, <Wn>, <Wm>{, <shift> #<amount>} | A64 | 0 | 0 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd | ||
| 0x8B000000 | ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>} | A64 | 1 | 0 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd | ||
| 0x5EE08400 | ADD D<d>, D<n>, D<m> | A64 | 01 | 0 | 11110 | 11 | 1 | Rm | 10000 | 1 | Rn | Rd | ||
| 0x0E208400 | ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | size | 1 | Rm | 10000 | 1 | Rn | Rd | ||
| 0xC120A300 | ADD { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101000 | 11000 | Zdn | 0 | ||
| 0xC120AB00 | ADD { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101010 | 11000 | Zdn | 0 | 0 | ||
| 0x04000000 | ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 000 | 00 | 0 | 000 | Pg | Zm | Zdn | ||
| 0x2520C000 | ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} | A64 | 00100101 | size | 100 | 00 | 0 | 11 | sh | imm8 | Zdn | ||
| 0x04200000 | ADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 1 | Zm | 000 | 00 | 0 | Zn | Zd | ||
| 0xC1A01C10 | ADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } | A64 | 110000011 | sz | 1000000 | Rv | 111 | Zm | 01 | 0 | off3 |
Description
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
for e = 0 to elements-1
element1 = Elem[operand1, e, esize];
element2 = Elem[operand2, e, esize];
if sub_op then
Elem[result, e, esize] = element1 - element2;
else
Elem[result, e, esize] = element1 + element2;
V[d, datasize] = result;